Dynamic random access memory (DRAM) chips, formed of large arrays of capacitors with sub-micron features, are utilized for main memory in computer systems. DRAM is relatively inexpensive and high density, thereby enabling large amounts of DRAM to be integrated per device. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC).
Some DDR memory chips can be periodically recalibrated to adjust certain operating parameters for changes in operating conditions such as temperature and voltage. For example, DDR3 and DDR4 allow periodic recalibration of output buffer impedance, known as “ZQ calibration”, and DDR4 allows periodic internal reference voltage recalibration, known as “VREFDQ training”. Moreover, when the DRAM chips are included in dual inline memory modules (DIMMs) they may optionally include a data buffer that itself has timing parameters that need to be recalibrated.
For example, in DDR4 DRAM chips, the VREFDQ values are configured by a host DDR controller during initialization and may be recalibrated during operation. The VREFDQ values are configured via certain mode register set commands. VREFDQ is preferably retrained during operation as conditions change, such as the board heating up, power supply drift, etc. Retraining can be disruptive and cause poor performance when done through existing software mechanisms. Additionally, in order to update a VREFDQ value on DDR4 DRAM chips, the JEDEC specification requires a specific sequence of multiple mode register set commands, and does not allow other intervening DRAM commands during the sequence. The current JEDEC standard makes it difficult to utilize single-test mode register commands via scripting tools, such as Hardware Debug Tool, for example.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.